Level shifting is commonly required in integrated circuit designs to shift the level of a signal between different voltage domains. Differential level shifters, for example, are commonly used to shift the common mode voltage of a differential input signal to either a higher or a lower voltage that is required for a particular circuit that will be processing the differential input signal.
Particularly given the continued demand for faster circuit performance, differential level shifters, like other circuits, desirably must operate with as little rise and fall delay as possible. In many memory interfaces, for example, circuit delays must be minimized to the extent possible to maximize data transfer speeds. Differential level shifters are often used in memory interfaces, for example, to level shift to a lower voltage than the surrounding logic circuitry to accommodate low voltage memory devices.
In conventional level shifters, contention often exists on internal nodes of the circuit during switching, as a new state often tries to overpower the current state of an internal node. When there is a large difference between the voltage supply driving the input and the voltage supply driving the output, the contention takes longer to be resolved. Also, because of this contention, conventional designs are susceptible to not switching correctly in the event of an NFET/PFET device strength mismatch. A weak field effect transistor (FET) may not be able to overcome a stronger FET when attempting to switch, leaving internal nodes in an unknown state.
Therefore, a need exists in the art for an improved differential level shifter with reduced contention on internal nodes and less susceptibility to device strength mismatches.